1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for determining a control sequence based upon at least one post-process consideration.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using a patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used as, for example, a gate electrode structure for transistors. Many times, trench isolation structures are also formed across the substrate of the semiconductor wafer to isolate electrical areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The semiconductor wafer 105 typically includes a plurality of individual semiconductor die 103 arranged in a grid 150. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed across one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on single or multiple die 103 locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to FIG. 2, a flowchart depiction of an illustrative prior art process flow is provided. A manufacturing system may determine the type of product that is to be manufactured by processing wafers (block 210). This determination may be made by analyzing various factors, such as market demands, factory capacity, etc. Based upon the product that is to be manufactured, the manufacturing system may select a processing plan for performing a series of processes upon the wafers (block 220). The processing plan may include various process parameters, such as scheduling parameters, routing parameters, control settings of particular processing tools, etc. Based upon the processing plan, the manufacturing system may direct various factory components to perform a series of processes upon a batch of semiconductor wafers 105 (block 230).
The manufacturing system may acquire metrology data at various points in the series of processes, including at the end of processing of the wafers (block 240). Based upon metrology data and/or post-processing data, the manufacturing system may perform feedback adjustments to subsequently processed wafers (block 240). The feedback correction may include adjusting scheduling, routing and/or process parameters for processing wafers from subsequent batches or lots.
There are various problems associated with the state-of-the-art methodology. One of these problems includes the fact that current feedback corrections relating to scheduling of wafers are generally based upon individual tool performance. This may be problematic because processing tools may not operate consistently during different instances of operations. Generally, state-of-the-art analysis is based upon an assumption that tools generally behave substantially identically for a given process operation at various instances. This assumption may not hold true, resulting in errors relating to process analysis.
Additionally, unexplained variations in process results may occur. In other words, for a given operation, tools may not be sufficiently matched, and therefore, may not produce similar results across several operations. Hence, for a specific process routing sequence, results may contain unexplained variations in different executions of the same sequence. These unexplained variations may cause inefficiencies in feedback corrections (e.g., adjusting parameters relating to scheduling, routing, etc.), thereby reducing the yield and/or degrading the performance of the processed wafers. The state-of-the-art generally lacks efficient methods for adjusting the scheduling or routing of a set of wafers through a series of process steps based upon interaction between the various components relating to the process steps.
The present invention is directed to overcoming, or at least reducing, the effects of one or more of the problems set forth above.